Exynos: clock: Correct pwm source clk selection

MPLL is selected as the source clk of pwm by default

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Padmavathi Venna <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>

diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h
index a15960121ce4deffad6dfc39bd085a5833806b05..34d8bc31f4dea5503fd596dc433f598a87e24521 100644 (file)
--- a/board/samsung/smdk5250/setup.h
+++ b/board/samsung/smdk5250/setup.h
@@ -343,7 +343,7 @@
 #define TOP2_VAL               0x0110000
 
 /* CLK_SRC_PERIC0 */
-#define PWM_SEL                0
+#define PWM_SEL                6
 #define UART3_SEL      6
 #define UART2_SEL      6
 #define UART1_SEL      6